Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.
FormalPro ™ is a Mentor Graphics solution designed for gate level regression testing of ASICs and ICs with 100000 and more gates. FormalPro uses static formal validation techniques to prove that a design is functionally identical to its reference. It confirms that the previous and final states of the design are functionally equivalent and, in technical terms, completes this in a much shorter time than door level simulations.
Questa Advanced Simulator
Questa® Advanced Simulator combines advanced debug capability with high performance and simulation capabilities for complete Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF native support. Questa Advanced Simulator is the basic simulation and debugging engine of the Questa Verification Platform; is a comprehensive advanced validation platform capable of mitigating complex FPGA and SoC design validation risks.
Veloce accelerates block and full SoC RTL simulations at all stages of the design process. Veloce provides debug and pre-silicon testing at hardware speeds using real data during hardware and software designs.
Calibre IC Verification & Signoff
Mentor’s IC verification and sign-off includes not only traditional rule-based physical verification and parasitic extraction, but also new capabilities and automated technologies that help improve yield by enhancing the design itself with the following products: Calibre nmDRC, Calibre nmLVS
Calibre Design For Manufacturing
Calibre® LFD™ (Litho Friendly Design) is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation. Calibre LFD accurately models the impact of lithographic processes on “as-drawn” layout data to determine the actual “as-built” dimensions of fabricated gates and metal interconnects with the following products: Calibre LFD™, Calibre YieldAnalyzer, Calibre YieldEnhancer
Calibre Computational Lithography
Low k1 photolithography processes are driving up the complexity and data volume of RET applications in nanometer designs. At 45nm and beyond, more complex models and through-process-window correction and verification requirements significantly increase computational burden. Both the lithographic challenges and the computational complexity associated with the advanced process nodes create a need for advanced capabilities in computational lithography software and hardware. Additional functionalities are supported with the following products: Calibre OPCverify™,Calibre nmOPC, Calibre OPCpro™, Calibre OPCsbar™, Calibre WORKbench™
Calibre Mask Process Correction
The next few IC technology nodes will be more challenging than any other transition since the first integrated circuit. Until the 32 nm node, distortions involved in making the masks using 193 nm lithography were small and had little impact since mask features are four times larger than the actual features on a die. Traditional OPC has mainly addressed the wafer image transfer and only included mask making effects as a part of the overall OPC model. Additional functionalities are supported with the following products: Calibre MPCpro, Calibre nmMPC
Calibre Mask Data Preparation
Mentor’s Mask Data Preparation (MDP) solution is fully compatible with the Calibre platform, enabling you to complete all resolution enhancement processing and mask data format conversion tasks in one mask fabrication batch run using a single control language. Additional functionalities are supported with the following products: Calibre FRACTURE™, Calibre MDPmerge™, Calibre MDPverify™, Calibre MDPview™, Calibre® MAPI™, Calibre® MASKOPT™
Analog FastSPICE (AFS) Platform
AFS is the fastest digital and mixed design verification platform in nanometer IC designs. Currently, many companies have been using AFS tools to verify their designs that require large area and high speed (i.e. high-speed I/O, PLL, ADC/DAC, CMOS image sensor, RFIC and embedded memory etc…)
Questa Verification IP
Mentor’s Verification IP (VIP) is targeted to address power, performance, security and functional safety challenges/deliverables and provide a tool for the most comprehensive verification for the industry’s latest and most advanced protocols. Some important features of Mentor’s Questa® VIP include: Fully compliant with UVM Standard, Compatible with all popular industry simulators, Unencrypted Test Sequence Library, Verification Plans & Coverage
Questa Formal Verification Tools
Questa formal-based technologies offer a broad spectrum of formal solutions and applications which complement simulation in a number of key areas. Questa Formal Verification Apps boost verification efficiency and design quality by exhaustively addressing verification tasks which are difficult to complete with traditional methods, yet don’t require formal or assertion-based verification experience.
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
Quantix offers a total lifecycle solution for semiconductor test data analytics from initial device characterization— to automated yield and quality management—to RMA analysis. Quantix solutions provide engineers and managers with “semiconductor intelligence” that enables better decision making and process improvement.The products are all based on a common architecture and use model, which makes it easy to scale up your yield and quality management activities as your business grows.
EXOSTIV is an innovative analysis, verification and debug solution for FPGA boards.
It provides simulator-like visibility – up to 200,000 times more than JTAG-based tools – and fast debug turnaround time for standard and custom FPGA boards.
EXOSTIV cuts the debug and analysis time from months to weeks.
Ürünler ile ilgili web seminerler
Mentor’un deneyimli doğrulama teknolojileri uzmanı tarafından gerçekleştirilecek olan HDL simülasyon/doğrulama konularını işleyen dizi web seminerleri kapsamında, Modelsim HDL simülatörünün genel özellikleri ve kolaylık sağlayan pratik kullanım ipuçlarıyla ilgili bilgilendirmelerin yer aldığı bir web seminerdir.
OVL, PSL ve SVA hakkında bilgi verilecek, doğrulama amaçlı assertion code yazılması ve bunun ModelSim/Questa ile uygulanması konularına değinilen bir web seminerdir.