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HDL Designer

HDL Designer combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process.



Determining if design requirements are met implies you can track them from specification through RTL description and on to verification results—a best practice for any requirements-based design flow. ReqTracer lets you easily implement and track a requirements-driven project development process.


Tanner Custom IC Design Flow

A complete custom IC design environment to capture, implement, and drive simulation and physical verification with broad foundry support.


Tanner MEMS Design Flow

In today’s MEMS design world, integration is more important than ever. To compete in a high-efficiency, high-productivity marketplace, you need a toolset that has proven its ability to accelerate the design cycles of commercially successful projects. The Tanner MEMS design flow not only makes integration of MEMS devices with analog/mixed-signal processing circuitry easy but also delivers the tools you need to improve the manufacturability of MEMS devices.


Questa Verification IP

Questa Verification IP (QVIP) integrates seamlessly into all verification environments on any simulator with easy-to-use UVM architecture across all protocols, ensuring verification of block level, subsystem, and SoC designs.


Questa Verification Memory Models Portfolio

The Questa Verification IP Memory Models Portfolio includes an extensive range of ready-to-use DRAM and Flash memory protocols and memory models to increase productivity and accelerate verification signoff.


Oasys-RTL Synthesis

Oasys-RTL addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction and using integrated floorplanning and placement capabilities.


Aprisa Digital Implementation Solution

Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a detail-route-centric physical design platform for the modern SoC.

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PowerPro Power Analysis and Optimization Platform

PowerPro offers the most comprehensive set of features to RTL designers to “design-for-low-power”. It offers power estimation for both RTL and Gate-level designs, early power checks to quickly find power issues during RTL development and clock and memory gating to optimize the design for power.

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Vista Flow

The Vista Flow consists of the steps typically used by SoC architects, hardware engineers, and software engineers to create TLM Models, assemble and configure the system, simulate, verify and debug, analyze and optimize performance, and power and integrate with the software.

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